This invention relates to a semiconductor test system for testing semiconductor devices such as ICs and LSIs, and more particularly, to a comparator circuit to be used in a semiconductor test system for evaluating output signals of a semiconductor device under test when the semiconductor device output is in a high impedance state.
In testing semiconductor IC devices by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test produced in response to the test signals. The output (analog) signals are compared with predetermined threshold voltages by analog comparators to determine logical states thereof. The logical states in the output of the analog comparators are strobed, i.e., sampled by strobe signals with predetermined timings to be compared with expected logic data to determine whether the IC device functions correctly or not.
The present invention is directed to such an analog comparator and strobe circuit (collectively xe2x80x9ccomparatorxe2x80x9d) for evaluating output signals of the semiconductor device under test. An example of the comparator in the conventional technology is shown in the block diagram of FIG. 5. The comparator circuit of FIG. 5 is comprised of mainly analog comparators and strobe (detector) circuits. The comparator of FIG. 5 is followed by a logic comparator (not shown) to determine whether the output signals of the comparator match the expected logical states (expected values).
In FIG. 5, the comparator includes analog comparators 10 and 20, a high timing detector 50, a window timing detector 70, a low timing detector, a high impedance (HIZ) detector 80, and selectors 91 and 92. The HIZ detector 80 includes a high level HIZ detector and a low level HIZ detector. The analog comparators 10 and 20 are provided with an output signal Si of the semiconductor device under test (DUT) at corresponding input terminals.
The analog comparator 10 is also provided with a high threshold voltage VOH to determine whether the output signal Si of the DUT is higher than the threshold voltage VOH, i.e., a logic xe2x80x9c1xe2x80x9d or xe2x80x9chighxe2x80x9d. Thus, when the output signal Si of the DUT is lower than the threshold voltage VOH, the analog comparator 10 generates a fail signal FHi. The analog comparator 20 is also provided with a low threshold voltage VOL to determine whether the output signal Si of the DUT is lower than the low threshold voltage VOL, i.e., a logic xe2x80x9c0xe2x80x9d or xe2x80x9clowxe2x80x9d. Thus, when the output signal Si of the DUT is higher than the threshold voltage VOL, the analog comparator 20 generates a fail signal FLi. As shown in FIG. 5, the outputs of the analog comparators 10 and 20 are respectively connected to the high timing detector 50, the window timing detector 70, the low timing detector 60, and the high impedance (HIZ) detector 80.
The high timing detector 50 is to detect whether there exists a high level fail at the timing of the strobe signal STB1. Thus, the fail signal FHi from the analog comparator 10 is latched by the edge timing of the strobe STB1, which is provided to the selector 91. The low timing detector 60 is to detect whether there exists a low level fail at the timing of the strobe signal STB2. Thus, the fail signal FLi from the analog comparator 20 is latched by the edge timing of the strobe STB1, and is provided to the selector 92.
The window timing detector 70 is to determine whether there exist any fails or glitches during a window period (time range) defined by the strobe signals STB1 and STB2. The window timing detector 70 is effective when a window strobe mode command xe2x80x9cWINDOW-MODExe2x80x9d is active. Generally, a glitch is a very short unwanted high amplitude transient that recurs irregularly in an electric system. When any high level fails or high level glitches are detected within the window period, a high glitch detection signal 70f1 is produced at the output of the detector 70, which is provided to the selector 91. When any low level fails or low level glitches are detected within the window period, a low glitch detection signal 70f2 is produced at the output of the detector 70, which is provided to the selector 92.
The high impedance (HIZ) detector 80 is to determine whether the subject pin of the DUT is in a high impedance state at the timing of the strobe signals STB1 or STB2. The HIZ detector 80 is effective when a high impedance mode command xe2x80x9cHIZ-MODExe2x80x9d is active. Many semiconductor devices are designed to be able to set a high impedance state for certain pins thereof when, for example, such pins do not function as I/O pins. In such a high impedance state of a pin, the semiconductor device is designed so that the output signal Si of the pin remains within the voltage range between the high and low threshold voltages VOH and VOL.
In other words, when the subject pin of the DUT is properly in the high impedance mode, the analog comparators 10 and 20 generate the fail signals FHi and FLi. Thus, when the output of the analog comparator 10 is other than the fail signal FHi at the timing of the strobe signal STB1 or STB2, i.e., the output signal Si is higher than the high threshold voltage VOH, a fail signal is detected by the high HIZ detector. The fail signal is provided to the selector 91. Similarly, when the output of the analog comparator 20 is other than the fail signal FLi at the timing of the strobe signal STB1 or STB2, i.e., the output signal Si is lower than the low threshold voltage VOL, a fail signal is detected by the low HIZ detector. The fail signal is provided to the selector 92.
The selectors 91 and 92 selectively provide fail signals FHo and FLo to a logic comparator (not shown) wherein the fail signals are compared with expected value data generated by a test pattern generator in the semiconductor test system. The selectors 91 and 92 are preset to transfer the output signals of the high timing detector 50 and the low timing detector 60, respectively, when the mode commands are not given thereto. When the selectors 91 and 92 receive the mode command xe2x80x9cWINDOW-MODExe2x80x9d or xe2x80x9cHIZ-MODExe2x80x9d at their select signal inputs, the selectors 91 and 92 respectively select the corresponding outputs FHo or FLo of either from the window timing detector 70 or the HIZ detector 80.
In the foregoing conventional comparator, there is a limitation in detecting the fail or glitch in the high impedance mode. Such a limitation is explained in the following with reference to FIGS. 4A-4F. The high impedance mode command xe2x80x9cHIZ-MODExe2x80x9d of FIG. 4A is given to the HIZ detector 80. As noted above, in the high impedance mode, the HIZ detector 80 is able to detect glitches or other fails which exist at the time of the strobe signal STB1 or STB2. The other fails in this case mean that the voltage level in the output signal Si exceeds the voltage range defined by the threshold voltages VOH and VOL for a relatively longer period of time than glitches.
Thus, the glitch (voltage higher than the high level threshold voltage VOH) in the output signal Si of the DUT shown in FIG. 4B or other fails can be detected by latching the same at the timing of the strobe signal STB1. Similarly, the glitch (voltage lower than the low level threshold voltage VOL) of in the output signal Si in FIG. 4C or other fails can be detected by latching the same at the timing of the strobe signal STB1.
However, the glitches or other fails shown in FIGS. 4D-4F cannot be detected in the conventional technology, because they are not in the timings of the strobe signals STB1 or STB2. The voltage wave form of FIG. 4E in the output signal Si indicates a fail in the high impedance state since the voltage level is higher than the threshold voltage VOH. Such a high impedance fail cannot be detected because the HIZ detector 80 is not able to latch the fail by the timing of the strobe signal STB1 or STB2. Similarly, the HIZ detector 80 cannot latch the glitches of FIG. 4D and 4F.
To detect the glitches or other fails in the high impedance mode of the DUT, the timings of the strobe signals STB1 and STB2 must be continuously changed to cover a desired timing length during the high impedance mode. Such a scanning method of the strobe signals requires a long time to fully test the desired time length especially when the time length to be inspected is large. For example, in the case where the time length to be inspected is 100 xcexcs (microsecond) and each step for scanning the strobe signal is 50 ns (nanosecond), it is required to change the timings of the strobe signal two thousand (2,000) times.
As a consequence, the conventional comparator of FIG. 5 takes a substantially long time to fully evaluate the high impedance state of the output pin of the DUT, resulting in the deterioration of throughput in testing semiconductor devices. Furthermore, if a glitch occurs irregularly, it is virtually impossible to detect such a glitch.
Therefore, it is an object of the present invention to provide a comparator circuit to be used in a semiconductor test system which is capable of fully testing the output signal of a semiconductor device under test which is in a high impedance mode.
It is another object of the present invention to provide a comparator circuit to be used in a semiconductor test system which is capable of testing the output signal of the semiconductor device under test throughout the time range (window) specified by strobe signals.
It is a further object of the present invention to provide a comparator circuit to be used in a semiconductor test system which is capable of fully and quickly testing the output signal of the semiconductor device under test which is in a high impedance state.
It is a further object of the present invention to provide a comparator circuit to be used in a semiconductor test system which is capable of immediately detecting any deviations from the high impedance state or any glitches in the output of the DUT within the specified time range.
In the present invention, a comparator circuit includes a window high impedance detector which detects any glitches or fails in the output of the DUT when the DUT is in the high impedance state. The window high impedance detector is able to immediately detect such glitches or fails occur at any time during a time range (window period) specified by strobe signals.
In one aspect of the present invention, the comparator used in the semiconductor test system for testing a semiconductor device (DUT) includes a first analog comparator for receiving an output signal of the DUT and comparing the output signal with a high threshold voltage, a second analog comparator for receiving the output signal of the DUT and comparing the output signal with a low threshold voltage, and means for detecting a deviation from a high impedance state of the DUT throughout a specified time range and for producing a fail signal when the deviation is detected, wherein the deviation from the high impedance state is defined as a voltage of the output signal which exceeds a range between the high threshold voltage and the low threshold voltage.
In another aspect of the present invention, the comparator circuit in a semiconductor test system for testing a semiconductor device (DUT) includes a first analog comparator for receiving an output signal of the DUT and comparing the output signal with a high threshold voltage, a second analog comparator for receiving the output signal of the DUT and comparing the output signal with a low threshold voltage, a high timing detector connected to the first analog comparator for detecting a fail signal from the first analog comparator when the output signal of the DUT is lower than the high threshold voltage at a timing of a first strobe signal, a low timing detector connected to the second analog comparator for detecting a fail signal from the second analog comparator when the output signal of the DUT is higher than the low threshold voltage at a timing of a second strobe signal, a window timing detector connected to the first and second analog comparators for detecting a fail signal from the comparators during a time range defined by the first and second strobe signals, a high impedance detector connected to the first and second analog comparators for detecting a high impedance fail signal from the comparators at a timing of the first or second strobe signal, and a window high impedance detector connected to the first and second analog comparators for detecting a deviation from a high impedance state of the DUT during a time range specified by the first and second strobe signals.
The window high impedance detector includes an SR flip-flop which is provided with the first and second strobe signals to produce the specified time range defined by the first and second strobe signals, a first D flip-flop for latching a fail signal indicating the deviation from the high impedance state based on an output signal from the first analog signal, a second D flip-flop for latching a fail signal indicating the deviation from the high impedance state based on an output signal from the second analog signal, first gate means connected to the first analog comparator for supplying the output signal of the first analog comparator to the first D flip-flop within the specified time range, and second gate means connected to the second analog comparator for supplying the output signal of the second analog comparator to the second D flip-flop within the specified time range.
According to the present invention, the comparator circuit for a semiconductor test system is capable of fully testing the output signal of a semiconductor device under test in the high impedance mode. The comparator circuit can immediately detect glitches or fails occur in the output signal of the semiconductor device under test throughout the time range (window) specified by strobe signals. The comparator circuit of the resent invention is capable of fully and quickly testing the output signal of the semiconductor device under test in the high impedance state by immediately detecting any deviations from the high impedance state or any glitches within the specified time range.